Since a wide band gap semiconductor material such as silicon carbide has a higher dielectric withstand voltage than silicon, it is possible to increase impurity concentration in the substrate thereof and thus reduce resistance of the substrate as compared with the ease of using a silicon material. This resistance reduction in the substrate leads to a power loss reduction in switching operation of a power device. In addition, since the wide-gap semiconductor material has higher thermal conductivity and better mechanical strength than silicon, it is expected as a feasible material for a compact, low-loss, and high-efficiency power device.
Among power semiconductor devices using silicon carbide (silicon carbide power semiconductor devices), a metal-oxide semiconductor field effect transistor (MOSFET), which is a field-effect transistor formed with a metal-insulator-semiconductor junction, is broadly used.
In an n-type silicon carbide drift layer epitaxially grown on an n-type silicon carbide substrate, a conventional silicon carbide semiconductor device includes an n-type source region, a first p-type well region with p-type impurity concentration of about 1019 cm−3 formed under the source region, a second p-type well region with the p-type impurity concentration in a range from about 1016 cm−3 to 1017 cm−3 formed next to the source region in the lateral direction on the side of a gate contact, the concentration being lower than that of the first well region by two or more orders of magnitude, a p-plug region with the p-type impurity concentration in a range from about 5×1018 cm−3 to 1×1021 cm−3 formed on the side of a source contact, the region being a well contact region connected to the source contact, and a threshold value adjustment region with n-type impurity concentration in a range from about 1015 cm−3 to 1010 cm−3 formed on the source region (for example, refer to Patent Document 1).
Further, in an n-type silicon carbide drift layer epitaxially grown on an n-type silicon carbide substrate, another conventional silicon carbide semiconductor device includes an n-type source region, a second base region being the first p-type well region with p-type impurity concentration in a range from 1×1017 cm−3 to 5×1018 cm−3 formed under the source region, a first base region being the second p-type well region with the p-type impurity concentration in a range from 5×1015 cm−1 to 5×1018 cm−1 formed next to the source region in the lateral direction on the side of a gate electrode, the concentration being lower than that of the second base region, and an n-type high concentration layer with n-type impurity concentration formed on the bottom of the second base region, the concentration being higher than that of the silicon carbide drift layer (for example, refer to Patent Document 2).